Fpga Prototype Queuing Module for High Performance Atm Switching

| FPGA technology has been used for the development and implementation of a prototype input queuing module of the Illinois Pulsar-based Optical INTconnect (iPOINT) Asynchronous Transfer Mode (ATM) testbed. Pipeline techniques were extensively used to solve timing problems and increase throughput. This prototype queuing module has been fully tested for bandwidth of 100 Mbps. Introduction In this paper, we present the FPGA implementation of an input queuing module of iPOINT testbed [1]. This queuing module has been successfully prototyped on a XC4005-5 FPGA device and fully tested for bandwidth of 100Mbps. The CAD tools used are XACT fromXilinx Inc. and Design Architecture model of Mentor Graphics version 8.2. The iPOINT testbed consists of UNIX workstations connected via optical bers to a central Pulsar switch. The Pulsar switch uses input queuing and has a wordwide shift-register ring fabric [2]. The core of the switch is prototyped using a XC4013-5 device [3], as illustrated in Figure 1. Four ports operate at 100 Mbps and the trunk port operates at 400 Mbps, providing an aggregate throughput of 800 Mbps. The queuing module is placed at each input port of the switch. Function and Logic of the Queuing Module Besides handling the interface logic for the Pulsar switch, the queuing module executes the CRC check on the header of each incoming ATM cell, performs VPI/VCI translation, directs the switch which port a particular ATM cell should be sent to, and bu ers the input tra c in case of output con ict. Contending cells are dropped when the queue is full. Opto-electronic and electro-optic conversions and clock recovery are done by the AMD Taxi board [4] [5]. The queuing module is implemented as two components: a FIFO chip to store the contending cells and a XC4005-5 FPGA chip to handle the queuing module control logic. Figure 2 shows the logic diagram of this queuing module. Its operation is described by the following pseudo code: read_machine() { while (power is on) /* --procedure 1, parallel to procedure 2 --*/ { if !(entire header of ATM cell in fifo) set Idle = 0; /* indicate idle state to switch */ else { read header from fifo; /* pipeline stages 1-5: */ latch the header bytes into pipeline; enable header CRC check circuit; Update = 0; /* block lookup table update */ generate address word for lookup table; VPI/VCI translation; header CRC check and find syndrome; if (syndrome==0) { set Correct_cell=1; form new VPI/VCI; generate STATUS WORD; } else drop the wrong cell; Update = 1; /* enable table update */ } wait for SEND_DATA = 0; /* indicate switch can transmit this cell */ while ((SEND_DATA = 0) && (not (49th byte)) read data from fifo; /* 1 byte/cycle, totally 48 */ } /* --procedure 2, parallel to procedure 1 --*/ { if (Set_Lookup==1) /* indicate look table need to be updated */ { start three-stage pipeline procedure; if (Update==1) { generate table address; put data on Date_Bus; } /* 1st stage */ if (Update==1) enable Table_Write signal; /* 2nd stage */ if (Update==1) disable Table_Write signal; reset address and data buses; /* 3rd stage */ } } } } write_machine() { while(power is on) { if ((fifo can store entire ATM cell) && (new cell arrives)) { if (first byte of an atm cell) set CELL_FLAG = 0; else set CELL_FLAG = 1; /* mark the 1st byte */ latch ATM byte into pipeline; generate fifo write control signals; write ATM byte into fifo; } else drop this cell; wait for next cell; } }